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FEATURES

LTC3709 Fast 2-Phase, No RSENSETM, Synchronous DC/DC Controller with Tracking/Sequencing DESCRIPTIO
The LTC(R)3709 is a single output, dual phase, synchronous step-down switching regulator. The controller uses a constant on-time, valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. An internal phase-locked loop allows the LTC3709 to be synchronized to an external clock. A TRACK pin is provided for tracking or sequencing the output voltage among several LTC3709 chips or an LTC3709 and other DC/DC regulators. Soft-start is accomplished using an external timing capacitor. Fault protection is provided by an output overvoltage comparator and an optional short-circuit shutdown timer. The current limit level is user programmable. A wide supply range allows voltages as high as 31V to step down to 0.6V.
, LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6476589, 6144194, 5847554, 6177678, 6304066, 6580258, 6674274, 6462525, 6593724.
PolyPhaseTM Valley Current Mode Controller Synchronizable to an External Clock with PLL Coincident or Ratiometric Tracking Sense Resistor Optional 2% to 90% Duty Cycle at 200kHz tON(MIN) < 100ns True Remote Sensing Differential Amplifier High Efficiency at Both Light and Heavy Loads Power Good Output Voltage Monitor 0.6V 1% Reference Adjustable Current Limit Programmable Soft-Start and Operating Frequency Output Overvoltage Protection Optional Short-Circuit Shutdown Timer 32-Lead (5mm x 5mm) QFN Package
APPLICATIO S

Notebook Computers Power Supply for DSP, ASIC, Graphic Processors
TYPICAL APPLICATIO
5V 4.7F 1F 47.5k VCC DRVCC ION TRACK TG1 VRNG FCB BOOST1 100k 0.1F PGOOD RUN/SS 3.32k 100nF 680pF 20k SGND 10k VFB DIFFOUT 15k VOS VOS+
-
High Efficiency Dual Phase 1.5V/30A Step-Down Converter
1F 1F 10 324k PGND1 PGND2 10F 35V x3 HAT2168H 0.22F 1.22H
100 95 90
VIN 4.5V TO 28V
10k
SW1 SENSE1+
EFFICIENCY (%)
BG1
HAT2165H
EXTLPF SENSE1- INTLPF PGND1 ITH LTC3709 TG2 BOOST2 SW2 SENSE2+ BG2 SENSE2- PGND2 HAT2165H 0.22F HAT2168H
VIN
1.22H
VOUT 1.5V 30A
+
330F 2.5V x4
3709 TA01a
U
U
U
Efficiency and Power Loss
VIN = 12V 10 9 8 EFFICIENCY 7 6 5 4 3 POWER LOSS 2 1 0.1 1 10 LOAD CURRENT (A) 0 100
3709 TA01b
85 80 75 70 65 60 55 50 0.01
POWER LOSS (W)
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LTC3709
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Input Supply Voltage (VCC, DRVCC) ............ 7V to - 0.3V Boosted Topside Driver Supply Voltage (BOOST1, BOOST2) .................................. 37V to - 0.3V Switch Voltage (SW1, 2) ............................. 31V to - 1V SENSE1+, SENSE2+ Voltages ....................... 31V to - 1V SENSE1-, SENSE2- Voltages .................... 10V to - 0.3V ION Voltage ............................................... 31V to -0.3V (BOOST - SW) Voltages ..............................7V to - 0.3V RUN/SS, PGOOD Voltages .......................... 7V to - 0.3V TRACK Voltage ............................................7V to - 0.3V VRNG Voltage ................................. VCC + 0.3V to - 0.3V ITH Voltage ............................................... 2.7V to - 0.3V VFB Voltage .............................................. 2.7V to - 0.3V INTLPF, EXTLPF Voltages ........................ 2.7V to - 0.3V VOS+, VOS- Voltages ................................... 7V to - 0.3V FCB Voltage ................................................ 7V to - 0.3V Operating Temperature Range ................ - 40C to 85C Junction Temperature (Note 2) ............................ 125C Storage Temperature Range ................ - 65C to 125C
32 31 30 29 28 27 26 25 RUN/SS 1 ITH 2 VFB 3 TRACK 4 SGND 5 SGND 6 VOS- 7 DIFFOUT 8 9 10 11 12 13 14 15 16 33 24 SENSE1- 23 PGND1 22 BG1 21 DRVCC 20 BG2 19 PGND2 18 SENSE2- 17 VCC
VOS+
NC
TG2
SW2
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN
EXPOSED PAD IS SGND (PIN 33) MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 34C/ W
ORDER PART NUMBER LTC3709EUH
UH PART MARKING 3709
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL IQ PARAMETER Input DC Supply Current Normal Shutdown FB Pin Input Current Feedback Voltage Feedback Voltage Line Regulation Feedback Voltage Load Regulation Error Amplifier Transconductance On-Time Minimum On-Time Minimum Off-Time Main Control Loop
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = DRVCC = 5V, unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
2.4 25 ITH = 1.2V (Note 3) ITH = 1.2V (Note 3) VIN = 4V to 6.5V (Note 3) ITH = 0.5V to 2V (Note 3) ITH = 1.2V (Note 3) VIN = 20V, ION = 180A VIN = 20V, ION = 90A VIN = 20V, ION = 540A VIN = 20V, ION = 90A 1.3 90 180
SENSE2+
EXTLPF
INTLPF
BOOST2
SENSE1+
BOOST1
PGOOD
VRNG
SW1
TG1
FCB
ION
3 65 - 60 0.606 - 0.2 1.6 140 280 100 350
IFB VFB VFB(LINEREG) VFB(LOADREG) gm(EA) tON tON(MIN) tOFF(MIN)
- 35 0.594 0.600 0.02 - 0.12 1.45 116 233 45 250
2
U
mA A nA V %/V % mS ns ns ns ns
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WW
W
LTC3709
ELECTRICAL CHARACTERISTICS
SYMBOL VSENSE(MAX) PARAMETER Maximum Current Sense Threshold
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = DRVCC = 5V, unless otherwise noted.
CONDITIONS VRNG = 1V VRNG = 0V VRNG = VCC VRNG = 1V VRNG = 0V VRNG = VCC 8.5 - 8.5
MIN 124 86 177
TYP 144 101 202 - 60 - 40 - 80 10 - 10 1.4 3 2.3
MAX 166 119 234
UNITS mV mV mV mV mV mV
VSENSE(MIN)
Minimum Current Sense Threshold
VFB(OV) VFB(UV) VRUN/SS(ON) VRUN/SS(LE) VRUN/SS(LT) IRUN/SS(C) IRUN/SS(D) UVLO TG RUP TG RDOWN BG RUP BG RDOWN Tracking ITRACK VFB(TRACK)
Overvoltage Fault Threshold Undervoltage Fault Threshold RUN Pin Start Threshold RUN Pin Latchoff Enable Threshold RUN Pin Latchoff Threshold Soft-Start Charge Current Soft-Start Discharge Current Undervoltage Lockout TG Driver Pull-Up On-Resistance TG Driver Pull-Down On-Resistance BG Driver Pull-Up On-Resistance BG Driver Pull-Down On-Resistance TRACK Pin Input Current Feedback Voltage at Tracking Measured at VCC Pin TG High TG Low BG High BG Low ITH = 1.2V, VTRACK = 0.2V (Note 3) VTRACK = 0.1V, ITH = 1.2V (Note 3) VTRACK = 0.3V, ITH = 1.2V (Note 3) VTRACK = 0.5V, ITH = 1.2V (Note 3) VFB Rising VFB Falling VFB Falling VFB Returning VPGOOD = 7V IPGOOD = 5mA RUN/SS Pin Rising RUN/SS Pin Falling
12.5 - 12.5 2
% % V V V
0.8
- 0.5 0.8
- 1.2 2 3.9 2 1.5 3 1.5 -100
-3 4 4.2
A A V
-150 110 310 510 12.5 - 12.5
nA mV mV mV % % s %
90 290 490 8.5 - 8.5 100
100 300 500 10 - 10 3.5
PGOOD Output VFBH VFBL PG Delay VFB(HYS) IPGOOD VPGL Phase-Lock Loop IINTPLL_SOURCE IINTPLL_SINK IEXTPLL_SOURCE IEXTPLL_SINK VFCB(DC) VFCB(AC) tON(PLL)1 Internal PLL Sourcing Current Internal PLL Sinking Current External PLL Sourcing Current External PLL Sinking Current Forced Continuous Threshold Clock Input Threshold tON1 Modulation Range by External PLL Up Modulation Down Modulation tON2 Modulation Range by Internal PLL Up Modulation Down Modulation Measured with a DC Voltage at FCB Pin Measured with a AC Pulse at FCB Pin ION1 = 180A, VEXTPLL = 1.8V ION1 = 180A, VEXTPLL = 0.6V ION2 = 180A, VINTPLL = 1.8V ION2 = 180A, VINTPLL = 0.6V 1.9 1 186 20 - 20 20 - 20 2.1 1.5 233 58 233 58 2.3 2 A A A A V V ns ns ns ns PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Delay PGOOD Hysteresis PGOOD Leakage Current PGOOD Low Voltage
1 0.2 0.4
A V
80
tON(PLL)2
186
80
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LTC3709
ELECTRICAL CHARACTERISTICS
SYMBOL AV VOS CM CMRR ICL GBP SR VO(MAX) RIN PARAMETER Differential Gain Input Offset Voltage Common Mode Input Voltage Range Common Mode Rejection Ratio Output Current Gain Bandwidth Product Slew Rate Maximum High Output Voltage Input Resistance Differential Amplifier
The denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = DRVCC = 5V, unless otherwise noted.
CONDITIONS MIN 0.995 = 1mA, Input Referred; Gain = 1 IOUT = 1mA 0V < IN+ = IN- < 5V, IOUT = 1mA, Input Referred IOUT = 1mA RL = 2k IOUT = 1mA Measured at IN+ Pin IN+ = IN- = 1.2V, IOUT TYP 1.000 0.5 MAX 1.005 7 5 70 UNITS V/V mV V dB mA MHz V/s V k
0 45 10
40 2 5 VCC - 1.2 VCC - 0.8 80
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3709EUH: TJ = TA + (PD * 34C/W) Note 3: The LTC3709 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH).
Note 4: The LTC3709E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 5: RDS(ON) limit is guaranteed by design and/or correlation to static test.
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LTC3709 TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up
VRUN/SS 5V/DIV VOUT 1V/DIV SW1 5V/DIV SW2 5V/DIV
IL1 10A/DIV IL2 10A/DIV
1ms/DIV
Transient Response (CCM)
ILOAD 3A-18A VOUT 50mV/DIV VSW1 20V/DIV VSW2 20V/DIV 20s/DIV
3709 G04
EFFICIENCY (%)
Power Loss vs Load Current
10 VIN = 12V VOUT = 1.5V f = 220kHz
1
POWER LOSS (W)
95
EFFICIENCY (%)
QUIESCENT CURRENT (mA)
0.1
0.01
0.001 10 1000 10000 100 LOAD CURRENT (mA) 100000
3709 G07
UW
Continuous Current Mode (CCM)
Discontinuous Current Mode (DCM)
SW1 5V/DIV SW2 1V/DIV
3709 G01
2s/DIV
3709 G02
10s/DIV
3709 G03
Transient Response (DCM)
100
ILOAD 3A-18A VOUT 50mV/DIV VSW1 20V/DIV VSW2 20V/DIV 20s/DIV
3709 G05
Efficiency vs Load Current
VIN = 12V 95 VOUT = 1.5V f = 220kHz 90 85 80 75 70 65 60 55 50 10 100 1000 LOAD (mA) 10000 100000
3709 G06
Efficiency vs VIN
100
3.0
Quiescent Current at VCC = 5V
VOUT = 1.5V ILOAD = 10A f = 220kHz
2.8
2.6
90
2.4
85
2.2
80
4
8
12
16 VIN (V)
20
24
3709 G08
2.0 -40
-20
40 20 0 TEMPERATURE (C)
60
80
3709 G09
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LTC3709 TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Current at VCC = 5V
45 40
SHUTDOWN CURRENT (A)
1.5 1.6
EA LOAD REGULATION (%)
-20 40 20 0 TEMPERATURE (C) 60 80
3709 G11
35 30 25
1.3
EA gm (mS)
20 15 -40
1.2 -40 0 -40
-20
40 20 0 TEMPERATURE (C)
VFB Pin Input Current
-20 -25
RUN/SS THRESHOLD (V)
VFB PIN INPUT CURRENT (nA)
-30 -35 -40 -45 -50 -40
1.4
ARMED THRESHOLD (V)
-20
40 20 0 TEMPERATURE (C)
UVLO Threshold
4.5
CURRENT SENSE THRESHOLD (mV)
4.3
UVLO THRESHOLD (V)
ON-TIME (ns)
4.1
3.9
3.7
3.5 -40
-20
40 20 0 TEMPERATURE (C)
6
UW
60 80
3709 G10
Error Amplifier gm
0.4
EA Load Regulation
0.3
1.4
0.2
0.1
-20
40 20 0 TEMPERATURE (C)
60
80
3709 G12
RUN/SS Threshold
1.8 4.0
Armed Threshold
1.6
3.5
3.0
1.2
1.0
2.5
60
80
3709 G13
0.8 -40
-20
40 20 0 TEMPERATURE (C)
60
80
3709 G14
2.0 -40
-20
40 20 0 TEMPERATURE (C)
60
80
3709 G15
On-Time vs ION Current
10000
300 250 200 150
Current Sense Threshold vs ITH Voltage
VRNG = 2V VRNG = VCC VRNG = 1V VRNG = 0V 100 50 0 -50 -100 -150 0 0.6 1.2 ITH VOLTAGE (V)
3709 G17
3709 G18
1000
100
VRNG = 0.5V
10
60 80
3709 G16
10
100 ION CURRENT (A)
1000
1.8
2.4
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LTC3709 TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Current Sense Threshold Voltage vs VRNG
350 300
MAXIMUM CURRENT SENSE THRESHOLD VOLTAGE (mV)
250 200 150 100 50 0 0.5
MINIMUM CURRENT SENSE THRESHOLD VOLTAGE (mV)
0.8
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.5s/F) and the time delay for overcurrent latch-off (see Applications Information). Forcing this pin below 1.4V shuts down the device. ITH (Pin 2): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). VFB (Pin 3): Error Amplifier Feedback Input. This pin connects to the error amplifier input. It can be used to attach additional compensation components if desired. TRACK (Pin 4): Tie the TRACK pin to a resistive divider connected to the output of another LTC3709 for either coincident or ratiometric output tracking (see Applications Information). To disable this feature, tie the pin to VCC. Do Not Float this pin. SGND (Pins 5, 6, 33): Signal Ground. All small-signal components such as CSS and compensation components should connect to this ground and eventually connect to PGND at one point. The Exposed Pad of the QFN package must be soldered to PCB ground. VOS- (Pin 7): The (-) Input to the Differential Amplifer. DIFFOUT (Pin 8): The Output of the Differential Amplifier. VOS+ (Pin 9): The (+) Input to the Differential Amplifier. EXTLPF (Pin 10): Filter Connection for the PLL. This PLL is used to synchronize the LTC3709 with an external clock. INTLPF (Pin 11): Filter Connection for the PLL. This PLL is use to phase shift the second channel to the first channel by 180. NC (Pin 12): No Connect.
UW
1.1
Minimum Current Sense Threshold Voltage vs VRNG
0 -20 -40 -60 -80 -100 -120 -140 0.5
1.4
1.7
2.0
3709 G19
0.8
1.1
1.4
1.7
2.0
3709 G20
VRNG (V)
VRNG (V)
U
U
U
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LTC3709
PI FU CTIO S
VCC (Pin 17): Main Input Supply. Decouple this pin to SGND with an RC filter (1, 0.1F). DRVCC (Pin 21): Driver Supply. Provides supply to the driver for the bottom gate. Also used for charging the bootstrap capacitor. BG1, BG2 (Pins 22, 20): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRVCC. PGND1, PGND2 (Pins 23, 19): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (-) terminal of CDRVCC and the (-) terminal of CIN. SENSE1-, SENSE2 - (Pins 24, 18): Current Sense Comparator Input. The (-) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. SENSE1+, SENSE2+ (Pins 25, 16): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information). SW1, SW2 (Pins 26, 15): Switch Node. The (-) terminal of the bootstrap capacitor CB connects here. This pin swings from a Schottky diode voltage drop below ground up to VIN. TG1, TG2 (Pins 27, 14): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to DRVCC superimposed on the switch node voltage SW. BOOST1, BOOST2 (Pins 28, 13): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below DRVCC up to VIN + DRVCC. PGOOD (Pin 29): Power Good Output. Open-drain logic output that is pulled to ground when output voltage is not within 10% of the regulation point. The output voltage must be out of regulation for at least 100s before the power good output is pulled to ground. ION (Pin 30): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. FCB (Pin 31): Forced Continuous and External Clock Input. Tie this pin to ground to force continuous synchronous operation or to VCC to enable discontinuous mode operation at light load. Feeding an external clock signal into this pin will synchronize the LTC3709 to the external clock and enable forced continuous mode. VRNG (Pin 32): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be programmed from 0.5V to 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to VCC.
8
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U
U
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LTC3709
FU CTIO AL DIAGRA
FCB CLOCK DETECTOR
FROM CHANNEL 2 TG EXTLPF PLL2 PLL1
OST tON = 0.7 (30pF) IION
R Q S 20k
+
ICMP
-
DUPLICATE FOR SECOND CHANNEL
1.4V VRNG SHDN TO CHANNEL 2 SWITCH LOGIC
x
0.7V 3.3A OV
1 240k ITH
EA
Q4
UV
RC SHED
ITHB TRACK Q1 Q2 0.6V VREF Q3
RUN SHDN 1.2A 6V
-+
1.4V RUN/SS
+ -
1.4V
CSS
+
CC
-
-
+
-
+
W
INTLPF ION RON
U
U
+
CIN 0.6V REF VCC
VIN
+
CVCC
TO CHANNEL 2 OST FCNT ON
BOOST TG SW L1 SWITCH LOGIC SENSE+ DRVCC SHDN OV BG PGND SENSE- 5V DB VOUT CB M1
+
IREV
+
COUT CDRVCC M2
-
0.66V VFB R2
SGND
R1
0.54V 100s BLANKING
PGOOD
40k VOS
+
40k
+ -
DISABLE DIFFOUT
VOS-
40k
40k
3709 FD
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LTC3709
OPERATIO
MAIN CONTROL LOOP The LTC3709 is a constant on-time, current mode stepdown controller with two channels operating 180 degrees out of phase. In normal operation, each top MOSFET is turned on for a fixed interval determined by its own oneshot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and repeating the cycle. The trip level of the current comparator is set by the ITH voltage, which is the output of error amplifier EA. Inductor current is determined by sensing the voltage between the SENSE - and SENSE+ pins using either the bottom MOSFET on-resistance or a separate sense resistor. At light load, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV, which then shuts off the bottom MOSFET, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled when the FCB pin is tied to ground, forcing continuous synchronous operation. The main control loop is shut down by pulling the RUN/SS pin low, turning off both top MOSFET and bottom MOSFET. Releasing the pin allows an internal 1.2A current source to charge an external soft-start capacitor CSS. When this voltage reaches 1.4V, the LTC3709 turns on and begins operating with a clamp on the noninverting input of the error amplifier. This input is also the reference input of the error amplifier. As the voltage on RUN/SS continues to rise, the voltage on the reference input also rises at the same rate, effectively controlling output voltage slew rate. Operating Frequency The operating frequency is determined implicitly by the top MOSFET on time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
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(Refer to Functional Diagram)
holding the frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this condition, the top MOSFET is turned off and the bottom MOSFET is turned on and held on until the condition is cleared. Power Good (PGOOD) Pin Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a 10% window around the regulation point. In addition, the output feedback voltage must be out of this window for a continuous duration of at least 100s before the PGOOD is pulled low. This is to prevent any glitch on the feedback voltage from creating a false power bad signal. The PGOOD will indicate a good power immediately when the feedback voltage is in regulation. Short-Circuit Detection and Protection After the controller has been started and been given adequate time to charge the output capacitor, the RUN/SS capacitor is used in a short-circuit time-out circuit. If the output voltage falls to less than 67% of its nominal output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latch off can be overridden by providing a >5A pull-up at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during an overcurrent and/or shortcircuit condition.
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LTC3709
OPERATIO
DRVCC
Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the DRVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from DRVCC through an external Schottky diode DB when the top MOSFET is turned off. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT+ and VOUT- benefits regulation in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground, preventing the possibility of troublesome "ground loops" on the PC layout and preventing voltage errors caused by board-to-board interconnects.
U
(Refer to Functional Diagram)
Dual Phase Operation An internal phase-lock loop (PLL1) ensures that channel 2 operates exactly at the same frequency as channel 1 and is also phase shifted by 180, enabling the LTC3709 to operate optimally as a dual phase controller. The loop filter connected to the INTLPF pin provides stability to the PLL. For external clock synchronization, a second PLL (PLL2) is incorporated into the LTC3709. PLL2 will adjust the ontime of channel 1 until its frequency is the same as the external clock. When locked, the PLL2 aligns the turn on of the top MOSFET of channel 1 to the rising edge of the external clock. Compensation for PLL2 is through the EXTLPF pin. Second Channel Shutdown During Light Loads When FCB is tied to VCC, discontinuous mode is selected. In this mode, no reverse current is allowed. The second channel is off when ITH is less than 0.8V for better efficiency. When FCB is tied to ground, forced continuous mode is selected, both channels are on and reversed current is allowed.
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LTC3709
APPLICATIO S I FOR ATIO
The basic LTC3709 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum load current and begins with the selection of the power MOSFET switches and/or sense resistor. The inductor current is determined by the RDS(ON) of the synchronous MOSFET while the user has the option to use a sense resistor for a more accurate current limiting. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across the RDS(ON) of the synchronous MOSFET or through a sense resistance that appears between the SENSE - and the SENSE+ pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately VRNG/7.5. The current mode control loop will not allow the inductor current valleys to exceed VRNG/(7.5 * RSENSE). In practice, one should allow some margin for variations in the LTC3709 and external component values. A good guide for selecting the sense resistance for each channel is:
RSENSE = 2 * VRNG 10 * IOUT(MAX)
The voltage of the VRNG pin can be set using an external resistive divider from VCC between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to ground or VCC, in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.3 times this nominal value. Connecting the SENSE + and SENSE - Pins The LTC3709 provides the user with an optional method to sense current through a sense resistor instead of using the RDS(ON) of the synchronous MOSFET. When using a sense resistor, it is placed between the source of the synchronous MOSFET and ground. To measure the voltage across
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this resistor, connect the SENSE+ pin to the source end of the resistor and the SENSE- pin to the other end of the resistor. The SENSE+ and SENSE- pin connections provide the Kelvin connections, ensuring accurate voltage measurement across the resistor. Using a sense resistor provides a well-defined current limit, but adds cost and reduces efficiency. Alternatively, one can use the synchronous MOSFET as the current sense element by simply connecting the SENSE+ pin to the switch node SW and the SENSE- pin to the source of the synchronous MOSFET, eliminating the sense resistor. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed in the Power MOSFET Selection section. Power MOSFET Selection The LTC3709 requires four external N-channel power MOSFETs, two for the top (main) switches and two for the bottom (synchronous) switches. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V DRVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3709 applications. If the driver's voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be used. When the bottom MOSFETs are used as the current sense elements, particular attention must be paid to their onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. In this case additional margin is required to accommodate the rise in MOSFET on-resistance with temperature:
W
UU
RDS(ON)(MAX) =
RSENSE T
The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C. Junction-tocase temperature is about 20C in most applications. For a maximum junction temperature of 100C, using a value 100C = 1.3 is reasonable (Figure 1).
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APPLICATIO S I FOR ATIO
2.0
T NORMALIZED ON-RESISTANCE
1.5
1.0
0.5
0 - 50
50 100 0 JUNCTION TEMPERATURE (C)
150
3709 F01
Figure 1. RDS(ON) vs Temperature
The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3709 is operating in continuous mode, the duty cycles for the MOSFETs are:
DTOP = DBOT VOUT VIN V -V = IN OUT VIN
The maximum power dissipation in the MOSFETs per channel is:
IOUT(MAX) PTOP = DTOP * * T(TOP) * RDS(ON)(MAX) + 2 I (0.5) * VIN2 * OUT * CRSS * f * 2 1 1 + RDS(ON)_ DRV VGS(TH) DRVCC - VGS(TH)
2
(
)
IOUT(MAX) PBOT = DBOT * * T(BOT) * RDS(ON)(MAX) 2
2
Both top and bottom MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are the largest at maximum input voltages. The
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bottom MOSFET losses are the greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs' "on" resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low "on" resistance with significantly reduced input capacitance for the main switch application in switching regulators. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of LTC3709 applications is determined implicitly by the one-shot timer that controls the on time, tON, of the top MOSFET switch. The on-time is set by the current into the ION pin according to:
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tON =
0.7 (30pF ) IION
Tying a resistor from VIN to the ION pin yields an on-time inversely proportional to VIN. For a down converter, this results in approximately constant frequency operation as the input supply varies:
f=
VOUT 0.7 * RON (30pF )
PLL and Frequency Synchronization In the LTC3709, there are two on-chip phase-lock loops (PLLs). One of the PLLs is used to achieve frequency locking and phase separation between the two channels while the second PLL is for locking onto an external clock. Since the LTC3709 is a constant on-time architecture, the error signal generated by the phase detector of the PLL is
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LTC3709
APPLICATIO S I FOR ATIO
used to vary the on-time to achieve frequency locking and 180 phase separation. The synchronization is set up in a "daisy chain" manner whereby channel 2's on-time will be varied with respect to channel 1. If an external clock is present, then channel 1's on-time will be varied and channel 2 will follow suit. Both PLLs are set up with the same capture range and the frequency range that the LTC3709 can be externally synchronized to is between 2 * fC and 0.5 * fC, where fC is the initial frequency setting of the two channels. It is advisable to set initial frequency as close to external frequency as possible. A limitation of both PLLs is when the on-time is close to the minimum (100ns). In this situation, the PLL will not be able to synchronize up in frequency. To ensure proper operation of the internal phase-lock loop when no external clock is applied to the FCB pin, the INTLPF pin may need to be pulled down while the output voltage is ramping up. One way to do this is to connect the anode of a silicon diode to the INTLPF pin and its cathode to the PGOOD pin and connect a pull-up resistor between the PGOOD pin and VCC. Refer to Figure 9 for an example. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current:
V V IL = OUT 1 - OUT f *L VIN
Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX)/2. Note that the largest ripple current occurs at the highest VIN. To guarantee that
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ripple current does not exceed a specified maximum, the inductance should be chosen according to:
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VOUT V L= 1 - OUT f * IL(MAX) VIN(MAX)
Once the value for L is known, the inductors must be selected (based on the RMS saturation current ratings). A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Toko and Panasonic. Schottky Diode Selection The Schottky diodes conduct during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which causes a modest (about 1%) efficiency loss. The diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between the diode and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection In continuous mode, the current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 2 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the input voltage is twice the output voltage.
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APPLICATIO S I FOR ATIO
In the Figure 2 graph, the local maximum input RMS capacitor currents are reached when:
VOUT 2k - 1 = where k = 1, 2 VIN 4
These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor 2 due to the effective increase in the frequency of the current pulses.
0.6 0.5
DC LOAD CURRENT
RMS INPUT RIPPLE CURRNET
0.4 0.3 0.2 0.1 0
1-PHASE 2-PHASE
0.1
0.2
0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN)
0.8
0.9
3709 F02
Figure 2. RMS Input Current Comparison
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The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by:
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1 VOUT IL ESR + 8 fCOUT
Since IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and longterm reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. Note that the average voltage across CB is approximately DRVCC. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + DRVCC. The boost capacitor
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LTC3709
APPLICATIO S I FOR ATIO
needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1F to 0.47F is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin to VCC enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which inductor current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current. The ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. Tying the FCB pin to ground forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. Besides providing a logic input to force continuous operation, the FCB pin acts as the input for external clock synchronization. Upon detecting a TTL level clock and the frequency is higher than the minimum allowable, channel 1 will lock on to this external clock. This will be followed by channel 2 (see PLL and Frequency Synchronization). The LTC3709 will be forced to operate in forced continuous mode in this situation. Fault Conditions: Current Limit The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3709, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is:
VSNS(MAX) 1 ILIMIT = + * IL * 2 RDS(ON) * T 2
The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
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generally occurs with the largest VIN at the highest ambient temperature, conditions which cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed junction temperature and the resulting value of ILIMIT, which heats the junction. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. For a more accurate current limiting, a sense resistor can be used. Sense resistors in the 1W power range are easily available with 5%, 2% or 1% tolerance. The temperature coefficient of these resistors are very low, ranging from 250ppm/C to 75ppm/C. In this case, the denominator in the above equation can simply be replaced by the RSENSE value. Minimum Off-Time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3709 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation in order to maintain the duty cycle at its limit. The minimum input voltage to avoid dropout is:
VIN(MIN) = VOUT 1 1 - tOFF(MIN) * f
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A plot of maximum duty cycle vs frequency is shown in Figure 3.
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LTC3709
APPLICATIO S I FOR ATIO
2.0
SWITCHING FREQUENCY (MHz)
1.5 DROPOUT REGION 1.0
0.5
0 0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) 1.0
3709 F03
Figure 3. Maximum Switching Frequency vs Duty Cycle
Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3709 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 1.4V puts the LTC3709 into a low quiescent current shutdown (IQ < 30A). Releasing the pin allows an internal 1.2A internal current source to charge the external capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about:
tDELAY = 1.4V * CSS = ( 1.2 s / F )CSS 1.2A
When the RUN/SS voltage reaches the ON threshold (typically 1.4V), the LTC3709 begins operating with a clamp on EA's reference voltage. The clamp level is one ON threshold voltage below RUN/SS. As the voltage on RUN/SS continues to rise, EA's reference is raised at the same rate, achieving monotonic output voltage soft-start (Figure 4). When RUN/SS rises 0.6V above the ON threshold, the reference clamp is invalidated and the internal precision reference takes over. After the controller has been started and given adequate time to charge the output capacitor, CSS is used as a shortcircuit timer. After the RUN/SS pin charges above 3V, and
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RUN/SS V = 0.6V ON THRESHOLD TIME VOUT1 TIME
3709 F04
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Figure 4. Monotonic Soft-Start Waveforms
if the output voltage falls below 67% of its regulated value, then a short-circuit fault is assumed. A 2A current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 2.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 3V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 -4 [F/VS]) Overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current of >5A to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to VIN as shown in Figure 5 is simple, but slightly increases shutdown current. Any pull-up network must be able to pull RUN/SS above the 3V threshold that arms the latchoff circuit and overcome the 2A maximum discharge current.
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LTC3709
APPLICATIO S I FOR ATIO
VCC RSS* RUN/SS RSS* D2* RUN/SS VIN 3.3V OR 5V D1
2N7002 CSS
*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF
(5a)
(5b)
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
Output Voltage Tracking The feedback voltage, VFB, will follow the TRACK pin voltage when the TRACK pin voltage is less than the reference voltage, VREF (0.6V). When the TRACK pin voltage is greater than VREF, the feedback voltage will servo to VREF. When selecting components for the TRACK pin, ensure the final steady-state voltage on the TRACK pin is greater than VREF at the end of the tracking interval. The LTC3709 allows the user to set up start-up sequencing among different supplies in either coincident tracking or ratiometric tracking as shown in Figure 6. To implement the coincident tracking, connect an extra resistor divider to the output of supply 1. This resistor divider is selected
OUTPUT VOLTAGE
VOUT2
OUTPUT VOLTAGE
TIME
(6a) Coincident Tracking
Figure 6. Two Different Forms of Output Voltage Sequencing
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CSS
3709 F05
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to be the same as the divider across supply 2's output. The TRACK pin of supply 2 is connected to this extra resistor divider. For the ratiometric tracking, simply connect the TRACK pin of supply 2 to the VFB pin of supply 1. Figure 7 shows this implementation. Note that in the coincident tracking, output voltage of supply 1 has to be set higher than output voltage of supply 2. Note that since the shutdown trip point varies from part to part, the "slave" part's RUN/SS pin will need to be connected to VCC. This eliminates the possibility that different LTC3709s may shut down at different times. If output sequencing is not needed, connect the TRACK pins to VCC. Do Not Float these pins.
SUPPLY 1 VOUT1 R1 VFB R2 R4 R3 VFB TRACK SUPPLY 2 LTC3709 VOUT2 R5
R6
3709 F07
R3 = R5 V COINCIDENTLY TRACKS VOUT1 R4 R6 OUT2 R3 = R1 RATIOMETRIC POWER UP R4 R2 BETWEEN VOUT1 AND VOUT2
Figure 7. Setup for Coincident and Ratiometric Tracking
VOUT1
VOUT1
VOUT2
TIME
3709 F06
(6b) Ratiometric Tracking
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LTC3709
APPLICATIO S I FOR ATIO
Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3709 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 0.1% up to 10% as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss (0.5) * VIN2 * IOUT * CRSS * f * 1 1 RDS(ON)_ DRV + DRVCC - VGS(TH) VGS(TH) 3. Gate driver supply current. The driver current supplies the gate charge QG required to switch the power MOSFETs. This current is typically much larger than the control circuit current. In continuous mode operation: IGATECHG = f (Qg(TOP) + Qg(BOT)) 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from
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causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problems. The ITH pin external components shown in Figure 9 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Design Example As a design example, take a supply with the following specifications: VIN = 7V to 28V (15V nominal), VOUT = 2.5V, IOUT(MAX) = 20A, f = 250kHz. First, calculate the timing resistor:
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RON =
2.5V = 476k (0.7V)(250kHz)(30pF )
and choose the inductor for about 40% ripple current at the maximum VIN. Maximum output current for each channel is 10A:
L=
2.5V 2.5V 1- = 2.3H (250kHz)(0.4)(10A) 28V
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LTC3709
APPLICATIO S I FOR ATIO
Selecting a standard value of 1.8H results in a maximum ripple current of:
2.5V 2.5V IL = 1- = 5.1A (250kHz)(1.8H) 28V
Next, choose the synchronous MOSFET switch. Choosing a Si4874 (RDS(ON) = 0.0083 (NOM) 0.010 (MAX), qJA = 40C/W) yields a nominal sense voltage of: VSNS(NOM) = (10A)(1.3)(0.0083) = 108mV Tying VRNG to 1.1V will set the current sense voltage range for a nominal value of 110mV with current limit occurring at 146mV. To check if the current limit is acceptable, assume a junction temperature of about 80C above a 70C ambient with 150C = 1.5:
146mV 1 ILIMIT + (5.1A) * 2 = 24A (1.5)(0.010) 2
and double check the assumed TJ in the MOSFET: PBOT 28 V - 2 .5V 24A = (1.5 )(0.010 ) = 1.97 W 2 28 V
2
TJ = 70C + (1.97W)(40C/W) = 149C Because the top MOSFET is on for such a short time, an Si4884 RDS(ON)(MAX) = 0.0165, CRSS = 100pF, JA = 40C/W will be sufficient. Checking its power dissipation at current limit with 100C = 1.4:
PTOP 2.5V 24A = (1.4)(0.0165) + 28 V 2
2
(1.7)(28V)2 (12A)(100pF )(250kHz)
= 0.30W + 0.40W = 0.7W
TJ = 70C + (0.7W)(40C/W) = 98C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 10A at 85C. The output capacitors are chosen for a low ESR of 0.013 to minimize output voltage changes due to
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inductor ripple current and load steps. The ripple voltage will be only: VOUT(RIPPLE) = IL(MAX) (ESR) = (5.1A) (0.013) = 66mV However, a 0A to 10A load step will cause an output change of up to: VOUT(STEP) = ILOAD (ESR) = (10A) (0.013) = 130mV An optional 22F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 9. PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. * The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. * Place CIN, COUT, MOSFETs, D1, D2 and inductors all in one compact area. It may help to have some components on the bottom side of the board. * Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3709. Use several larger vias for power components. * Use a compact plane for switch node (SW) to keep EMI down. * Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. * Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 9.
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LTC3709
APPLICATIO S I FOR ATIO
* Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point, which is then tied to a "clean" point in the power ground such as the "-" node of CIN. * Minimize impedance between input ground and output ground. * Connect PGND1 to the source of M2 or RS1 (QFN) directly. This also applies to channel 2. * Place M2 as close to the controller as possible, keeping the PGND1, BG1 and SW1 traces short. The same for the other channel. SW2 trace should connect to the drain of M2 directly. * Connect the input capacitor(s) CIN close to the power MOSFETs: (+) node to drain of M1, (-) node to source of M2. This capacitor carries the MOSFET AC current.
D D D D
G S S S RSENSE MOSFET SENSE + SENSE - SENSE + SENSE -
3709 F08
(8a) Sensing the Bottom MOSFET
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* Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. * Connect the DRVCC decoupling capacitor CVCC closely to the DRVCC and PGND pins. * Connect the top driver boost capacitor CB closely to the BOOST and SW pins. * Connect the VIN pin decoupling capacitor CF closely to the VCC and PGND pins. * Are the SENSE- and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE- and SENSE+ (CSENSE) should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor as shown in Figure 8.
(8b) Sensing a Resistor
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Figure 8. Kelvin Sensing
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LTC3709
APPLICATIO S I FOR ATIO
MMSD4148 (OPTIONAL) CSS 0.1F 1 CC 470pF 100pF 3 4 TRACK 100pF 5 6 7 RF2 10k RF1 31.6k 8 9 100nF 1nF 10 100nF 470pF 12 13 CB2 0.22F 14 15 16 3.32k 11 475 LTC3709EUH EXTLPF INTLPF NC BOOST2 TG2 SW2 SENSE2
+
RUN/SS ITH VFB TRACK SGND SGND VOS-
VRNG FCB ION PGOOD BOOST1 TG1 SW1
RC 20k
2
DIFFOUT SENSE1+ VOS+ SENSE1 -
PGND1 BG1 DRVCC BG2 PGND2 SENSE2 - VCC 100pF
L1, L2: PANASONIC ETQP6FIR8BFA COUT: PANASONIC EEFUEOG181R M1, M3: SILICONIX Si4884DY M2, M4: SILICONIX Si4874DY
Figure 9. 2-Phase 2.5V/20A Supply at 250kHz with Tracking and External Synch
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10nF 32 31 30 29 28 27 26 25 24 100pF 10k fIN RON 476k RPGOOD 100k PGOOD DB1 CMDSH-3 35.7k VIN 7V TO 28V DRVCC 5V D1 B340A CB1 0.22F M1 M2 L1 1.8H 23 22 21 20 19 18 17 10 M3 1F DB2 CMDSH-3 M4 L2 1.8H 1F 1F CIN 10F 35V x3 COUT 180F 4V x4 VOUT 2.5V 20A
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+
D2 B340A
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LTC3709
PACKAGE DESCRIPTIO
5.50 0.05 4.10 0.05 3.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 0.00 - 0.05
NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 0.23 TYP (4 SIDES) 3.45 0.10 (4-SIDES)
(UH) QFN 0603
0.200 REF
0.25 0.05 0.50 BSC
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LTC3709
TYPICAL APPLICATIO
CSS 0.1F CC 1nF 220pF 5V 4 5 6 RC 20k
1 2 3
RUN/SS ITH VFB TRACK SGND
RF2 10k
RF1 190k
100nF
3.32k 470pF
CB2 0.22F
27 SGND TG1 LTC3709 7 26 VOS- SW1 8 25 DIFFOUT SENSE1+ 9 24 SENSE1 - VOS+ 10 23 EXTLPF PGND1 11 22 INTLPF BG1 12 21 NC DRVCC 13 20 BG2 BOOST2 14 19 PGND2 TG2 15 18 SENSE2 - SW2 16 17 VCC SENSE2 + 100pF
RELATED PARTS
PART NUMBER LTC1708 LTC1778 LTC3413 LTC3708 LTC3728 LTC3729 DESCRIPTION Fast 2-Phase Dual Output Step-Down Controller Wide Operating Range, No RSENSE Step-Down Controller DDR, QDR Memory Termination Regulator Fast, Dual No RSENSE, 2-Phase Synchronous Step-Down Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator 550kHz, PolyPhase , High Efficiency, Synchronous Step-Down Switching Regulator
(R)
LTC3730/LTC3731 3-Phase to 12-Phase Synchronous Step-Down Controllers LTC3732 LTC3778 Wide Operating Range, No RSENSE Step-Down Controller PolyPhase is a registered trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
Low Output Ripple, 2-Phase 12V/30A Supply
VRNG FCB ION PGOOD BOOST1 32 31 30 29 28 RPGOOD 100k DB1 CMDSH-3 CB1 0.22F M1 M2 10nF RON 2.86M DRVCC 5V 10k 21.5k VIN 24V D1 B340A L1 4.7H TOKO FDA1254 COUT 150F 16V x3 100pF
+
1F CIN 10F 35V x3
VOUT
1F L2 4.7H DB2 CMDSH-3
10 1F M3 M4
D2 B340A M1-M4: RENESAS HAT2167 COUT: OS-CON 16SVP150M
3709 TA02
COMMENTS PLL, VIN up to 36V, Tracking Single Channel, GN16 Package 3A Output Current, 90% Efficiency Very Fast Transient Response; Very Low Duty Factor Tracking; Minimum CIN, COUT Fixed Frequency, Dual Output Fixed Frequency, Single Output, Up to 12-Phase Operation 40A to 240A, 4.5V VIN 32V, 0.6V VOUT 5V Single Channel, Separate VON Programming
3709f LT/TP 1104 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2004

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